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DATE
2008
IEEE
170views Hardware» more  DATE 2008»
14 years 2 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
ISQED
2006
IEEE
118views Hardware» more  ISQED 2006»
14 years 1 months ago
Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming
— In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linea...
Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici C...
TC
2008
13 years 7 months ago
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of irregular meshes is an im...
Shu-Yen Lin, Chun-Hsiang Huang, Chih-Hao Chao, Ken...
RTSS
2008
IEEE
14 years 2 months ago
Priority Assignment for Real-Time Wormhole Communication in On-Chip Networks
—Wormhole switching with fixed priority preemption has been proposed as a possible solution for real-time on-chip communication. However, none of current priority assignment pol...
Zheng Shi, Alan Burns
SBACPAD
2007
IEEE
130views Hardware» more  SBACPAD 2007»
14 years 1 months ago
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP)
In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switc...
Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh