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FPL
2007
Springer
120views Hardware» more  FPL 2007»
14 years 28 days ago
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays
In this paper, we propose a Dynamically Reconfigurable Processor Array (DRPA) generator which can generate various types of DRPAs. Our target DRPA architecture is fully parameter...
Yohei Hasegawa, Hideharu Amano
FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
14 years 2 days ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
FCCM
2003
IEEE
96views VLSI» more  FCCM 2003»
14 years 2 days ago
Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures
FPGAs have appealing features such as customizable internal and external bandwidth and the ability to exploit vast amounts of fine-grain parallelism. In this paper we explore the ...
Pedro C. Diniz, Joonseok Park
FPL
2007
Springer
190views Hardware» more  FPL 2007»
14 years 28 days ago
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...
Andreas Herrholz, Frank Oppenheimer, Philipp A. Ha...
FCCM
2005
IEEE
131views VLSI» more  FCCM 2005»
14 years 11 days ago
Automating the Layout of Reconfigurable Subsystems Using Circuit Generators
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
Shawn Phillips, Scott Hauck