4 search results - page 1 / 1 » Post-placement C-slow retiming for the xilinx virtex FPGA |
FPGA
2003
ACM
14 years 1 months ago
2003
ACM
FCCM
2002
IEEE
14 years 1 months ago
2002
IEEE
C-slow retiming (changing a design to support multiple instances of a computation) and datapath-aware placement have long been advocated by members of the FPGA synthesis community...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
FCCM
2009
IEEE
14 years 3 months ago
2009
IEEE
—Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SP...