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» Power Awareness in Network Design and Routing
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FPL
2007
Springer
100views Hardware» more  FPL 2007»
14 years 1 months ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton
ESOA
2006
13 years 11 months ago
ASOS: An Adaptive Self-organizing Protocol for Surveillance and Routing in Sensor Networks
We present a simple model of self-organization for sensor networks that addresses two conflicting requirements: hazard situations should be reported to a sink node with as little ...
Jorge Simão
INFOCOM
2005
IEEE
14 years 1 months ago
Topology aware overlay networks
— Recently, overlay networks have emerged as a means to enhance end-to-end application performance and availability. Overlay networks attempt to leverage the inherent redundancy ...
Junghee Han, David Watson, Farnam Jahanian
DATE
2004
IEEE
185views Hardware» more  DATE 2004»
13 years 11 months ago
Energy-Aware System Design for Wireless Multimedia
In this paper, we present various challenges that arise in the delivery and exchange of multimedia information to mobile devices. Specifically, we focus on techniques for maintain...
Hans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta...
EWSN
2006
Springer
14 years 7 months ago
On the Scalability of Routing Integrated Time Synchronization
Time synchronization is a crucial component of a large class of sensor network applications, traditionally implemented as a standalone middleware service that provides a virtual gl...
János Sallai, Branislav Kusy, Ákos L...