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100
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ISLPED
2009
ACM
100views Hardware» more  ISLPED 2009»
15 years 9 months ago
Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits
Post-fabrication tuning for mitigating manufacturing variability is receiving a significant attention. To reduce leakage increase involved in performance compensation by body bia...
Koichi Hamamoto, Masanori Hashimoto, Yukio Mitsuya...
167
Voted
VTS
2006
IEEE
133views Hardware» more  VTS 2006»
15 years 8 months ago
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
Minsik Cho, David Z. Pan
163
Voted
FPGA
2003
ACM
167views FPGA» more  FPGA 2003»
15 years 7 months ago
A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...
122
Voted
EENERGY
2010
15 years 6 months ago
Energy saving and network performance: a trade-off approach
Power consumption of the Information and Communication Technology sector (ICT) has recently become a key challenge. In particular, actions to improve energy-efficiency of Internet...
Carla Panarello, Alfio Lombardo, Giovanni Schembra...
129
Voted
VLSISP
2010
148views more  VLSISP 2010»
15 years 29 days ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...