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ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
14 years 3 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
RECOMB
2005
Springer
14 years 10 months ago
Power Boosts for Cluster Tests
Abstract. Gene cluster significance tests that are based on the number of genes in a cluster in two genomes, and how compactly they are distributed, but not their order, may be mad...
David Sankoff, Lani Haque
WISER
2004
ACM
14 years 3 months ago
Hardware/software co-design for power system test development
Many hardware/software co-design models have been proposed [7, 2, 5, 6] that attempt to address problems in the hardware/software interface, in partitioning the system between har...
Austin Armbruster, Matt Ryan, Xiaoqing Frank Liu, ...
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
13 years 11 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....
ICCD
2006
IEEE
84views Hardware» more  ICCD 2006»
14 years 6 months ago
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Y...