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CASES
2003
ACM
15 years 11 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
IEEEPACT
2006
IEEE
16 years 6 days ago
Core architecture optimization for heterogeneous chip multiprocessors
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to de...
Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
TVLSI
2002
102views more  TVLSI 2002»
15 years 5 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
VLSISP
2008
159views more  VLSISP 2008»
15 years 6 months ago
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
The compiler is generally regarded as the most important software component that supports a processor design to achieve success. This paper describes our application of the open re...
Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin...
CSREAESA
2003
15 years 7 months ago
Coarse-Grained DRAM Power Management
− This paper presents an efficient system level power saving method for DRAM with multiple power modes. The proposed method is based on the power aware scheduling algorithm that ...
Jin Hwan Park, Sarah Wu, Baback A. Izadi