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ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 10 days ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
CODES
2001
IEEE
13 years 11 months ago
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors
In this paper, we explore a hybrid global/local search optimization framework for dynamic voltage scaling in embedded multiprocessor systems. The problem is to find, for a multipr...
Neal K. Bambha, Shuvra S. Bhattacharyya, Jürg...
VLSISP
2008
95views more  VLSISP 2008»
13 years 7 months ago
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...
Tsu-Ming Liu, Chen-Yi Lee
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
14 years 1 months ago
A practical FPGA-based framework for novel CMP research
Chip-multiprocessors are quickly gaining momentum in all segments of computing. However, the practical success of CMPs strongly depends on addressing the difficulty of multithread...
Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy T...
SAS
2007
Springer
108views Formal Methods» more  SAS 2007»
14 years 1 months ago
Programming Language Design and Analysis Motivated by Hardware Evolution
Abstract. Silicon chip design has passed a threshold whereby exponentially increasing transistor density (Moore’s Law) no longer translates into increased processing power for si...
Alan Mycroft