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202
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CAMP
2005
IEEE
15 years 8 months ago
2005
IEEE
— We have simulated the implementation of 16-bit floating point instructions on a Pentium4 and PowerPC G4 and G5 to evaluate the performance impact of these instructions in embed...
153
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ISLPED
1996
ACM
15 years 10 months ago
1996
ACM
This paper proposes a 0.5V / 100MHz / sub-5mW-operated 1-Mbit SRAM cell architecture which uses an overVCC grounded data storage (OVGS) scheme. The key target of OVGS is to minimi...
149
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ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
Modern superscalar microprocessors need sizable register files to support large number of in-flight instructions for exploiting ILP. An alternative to building large register file...
180
Voted
HPDC
2010
IEEE
15 years 6 months ago
2010
IEEE
Massively multicore processors, like, for example, Graphics Processing Units (GPUs), provide, at a comparable price, a one order of magnitude higher peak performance than traditio...
144
Voted
PARELEC
2000
IEEE
15 years 10 months ago
2000
IEEE
The purpose of this paper is to demonstrate the implementation of an adaptable parallel architecture capable of system to task adaptation. The system implementation was based on X...