Sciweavers

296 search results - page 19 / 60
» Power Estimation in Sequential Circuits
Sort
View
ICCAD
2000
IEEE
73views Hardware» more  ICCAD 2000»
14 years 13 days ago
Simulation and Optimization of the Power Distribution Network in VLSI Circuits
In this paper, we present simulation techniques to estimate the worst-case voltage variation using a RC model for the power distribution network. Pattern independent maximum envel...
Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj
DAC
1994
ACM
14 years 4 days ago
Statistical Estimation of the Switching Activity in Digital Circuits
Higher levels of integration have led to a generation of integrated circuits for which power dissipation and reliability are major design concerns. In CMOS circuits, both of these ...
Michael G. Xakellis, Farid N. Najm
FOCS
2007
IEEE
13 years 12 months ago
Discrepancy and the Power of Bottom Fan-in in Depth-three Circuits
We develop a new technique of proving lower bounds for the randomized communication complexity of boolean functions in the multiparty `Number on the Forehead' model. Our meth...
Arkadev Chattopadhyay
DFT
1999
IEEE
131views VLSI» more  DFT 1999»
14 years 11 days ago
Optimal Vector Selection for Low Power BIST
In the last decade, researchers have devoted increasing efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption durin...
Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaud...
ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
14 years 5 months ago
Simultaneous power and thermal integrity driven via stapling in 3D ICs
The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first ...
Hao Yu, Joanna Ho, Lei He