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» Power Estimation in Sequential Circuits

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DFT
2007
IEEE

104views VLSI» more DFT 2007»

Reduction of Fault Latency in Sequential Circuits by using Decomposition

14 years 2 months ago

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The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...

Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky

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ASPDAC
2000
ACM

95views Hardware» more ASPDAC 2000»

FSM decomposition by direct circuit manipulation applied to low power design

14 years 14 days ago

Download www.cs.york.ac.uk

Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that signiﬁca...

José C. Monteiro, Arlindo L. Oliveira

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ICCAD
1996
IEEE

89views Hardware» more ICCAD 1996»

An algorithm for power estimation in switched-capacitor circuits

14 years 7 days ago

Download www.cs.ucr.edu

A number of low-power designs,such as those for mobile communicationequipment, containswitched-capacitorcircuits. In such designs it is important to be able to estimate the power ...

Chad Young, Giorgio Casinovi, Jonathan Fowler, Pau...

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DAC
1992
ACM

123views Computer Architecture» more DAC 1992»

Estimation of Average Switching Activity in Combinational and Sequential Circuits

14 years 5 days ago

Download www.cs.nthu.edu.tw

Abhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jac...

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