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» Power Macromodeling for High Level Power Estimation
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JSA
2010
158views more  JSA 2010»
13 years 2 months ago
Scalable mpNoC for massively parallel systems - Design and implementation on FPGA
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
Mouna Baklouti, Yassine Aydi, Philippe Marquet, Je...
TVCG
2010
151views more  TVCG 2010»
13 years 2 months ago
Interactive Visual Analysis of Multiple Simulation Runs Using the Simulation Model View: Understanding and Tuning of an Electron
Multiple simulation runs using the same simulation model with different values of control parameters usually generate large data sets that capture the variational aspects of the be...
Kresimir Matkovic, Denis Gracanin, Mario Jelovic, ...
BMCBI
2010
99views more  BMCBI 2010»
13 years 7 months ago
A statistical method for excluding non-variable CpG sites in high-throughput DNA methylation profiling
Background: High-throughput DNA methylation arrays are likely to accelerate the pace of methylation biomarker discovery for a wide variety of diseases. A potential problem with a ...
Hailong Meng, Andrew R. Joyce, Daniel E. Adkins, P...
BMCBI
2008
138views more  BMCBI 2008»
13 years 7 months ago
Systematic identification of yeast cell cycle transcription factors using multiple data sources
Background: Eukaryotic cell cycle is a complex process and is precisely regulated at many levels. Many genes specific to the cell cycle are regulated transcriptionally and are exp...
Wei-Sheng Wu, Wen-Hsiung Li