979 search results - page 19 / 196 » Power Macromodeling for High Level Power Estimation |
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
The clock tree is the interconnect net on Systems-on-Chip (SoCs) with the heaviest load and consumes up to 40% of the overall power budget. Substantial savings of the overall powe...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
DCC
2008
IEEE
13 years 9 months ago
2008
IEEE
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
ESTIMEDIA
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called ’event signatures’, op...