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» Power Macromodeling for High Level Power Estimation
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VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
14 years 1 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
ISVLSI
2007
IEEE
232views VLSI» more  ISVLSI 2007»
14 years 2 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
Nainesh Agarwal, Nikitas J. Dimopoulos
CLUSTER
2007
IEEE
13 years 11 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...
BMCBI
2011
13 years 2 months ago
Sequential Interim Analyses of Survival Data in DNA Microarray Experiments
Background: Discovery of biomarkers that are correlated with therapy response and thus with survival is an important goal of medical research on severe diseases, e.g. cancer. Freq...
Andreas Leha, Tim Beißbarth, Klaus Jung
TVLSI
2008
144views more  TVLSI 2008»
13 years 7 months ago
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective
Abstract--Embedded systems present significant security challenges due to their limited resources and power constraints. This paper focuses on the issues of building secure embedde...
Guy Gogniat, Tilman Wolf, Wayne P. Burleson, Jean-...