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» Power Macromodeling for High Level Power Estimation
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ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
14 years 2 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
JCP
2008
216views more  JCP 2008»
13 years 7 months ago
Design Overview Of Processor Based Implantable Pacemaker
Implantable pacemaker is a battery operated real time embedded system, which includes software/hardware codesign strategy. As it is placed within the heart by surgery, battery life...
Santosh D. Chede, Kishore D. Kulat
VLDB
2001
ACM
114views Database» more  VLDB 2001»
14 years 8 days ago
Distinct Sampling for Highly-Accurate Answers to Distinct Values Queries and Event Reports
Estimating the number of distinct values is a wellstudied problem, due to its frequent occurrence in queries and its importance in selecting good query plans. Previous work has sh...
Phillip B. Gibbons
TASLP
2008
117views more  TASLP 2008»
13 years 7 months ago
Auditory-Based Spectral Amplitude Estimators for Speech Enhancement
We propose a new family of Bayesian estimators for speech enhancement where the cost function includes both a power law and a weighting factor. The parameters of the cost function,...
Eric Plourde, Benoît Champagne