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» Power Macromodeling for High Level Power Estimation
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ISPD
2005
ACM
116views Hardware» more  ISPD 2005»
14 years 1 months ago
A fast algorithm for power grid design
This paper presents an efficient heuristic algorithm to design a power distribution network of a chip by employing a successive partitioning and grid refinement scheme. In an it...
Jaskirat Singh, Sachin S. Sapatnekar
ISQED
2007
IEEE
140views Hardware» more  ISQED 2007»
14 years 1 months ago
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
DATE
2002
IEEE
105views Hardware» more  DATE 2002»
14 years 18 days ago
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
Chunhong Chen, Majid Sarrafzadeh
CVPR
2011
IEEE
13 years 3 months ago
High Level Describable Attributes for Predicting Aesthetics and Interestingness
With the rise in popularity of digital cameras, the amount of visual data available on the web is growing exponentially. Some of these pictures are extremely beautiful and aesthet...
Sagnik Dhar, Vicente Ordonez, Tamara Berg