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» Power Optimization in Current Mode Circuits
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SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
14 years 1 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
TCAD
2010
107views more  TCAD 2010»
13 years 2 months ago
Evaluating Statistical Power Optimization
In response to the increasing variations in integrated-circuit manufacturing, the current trend is to create designs that take these variations into account statistically. In this ...
Jason Cong, Puneet Gupta, John Lee
INFOCOM
2005
IEEE
14 years 1 months ago
Smart power-saving mode for IEEE 802.11 wireless LANs
StaticPSM (Power-Saving Mode)schemes employed in the current IEEE 802.11 implementations could not provide any delag-performance guarantee because of their fixed wakeup intervals. ...
Daji Qiao, Kang G. Shin
ICCAD
2007
IEEE
130views Hardware» more  ICCAD 2007»
14 years 4 months ago
Analysis and optimization of power-gated ICs with multiple power gating configurations
- Power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. Disconnecting...
Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh ...
SAMOS
2007
Springer
14 years 2 months ago
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and
Abstract— This paper explores the resistance of MOS Current Mode Logic (MCML) against Differential Power Analysis (DPA) attacks. Circuits implemented in MCML, in fact, have uniqu...
Francesco Regazzoni, Stéphane Badel, Thomas...