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» Power Optimized Combinational Logic Design
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ASPDAC
2005
ACM
115views Hardware» more  ASPDAC 2005»
14 years 1 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
ASAP
2004
IEEE
115views Hardware» more  ASAP 2004»
13 years 11 months ago
A Low-Power Carry Skip Adder with Fast Saturation
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
Michael J. Schulte, Kai Chirca, John Glossner, Hao...
CORR
2010
Springer
158views Education» more  CORR 2010»
13 years 2 months ago
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
14 years 1 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann