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» Power Optimized Combinational Logic Design
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DLOG
2007
14 years 11 days ago
Exploiting Conjunctive Queries in Description Logic Programs
We present cq-programs, which enhance nonmonotonic description logics (dl-) programs by conjunctive queries (CQ) and union of conjunctive queries (UCQ) over Description Logics kno...
Thomas Eiter, Giovambattista Ianni, Thomas Krennwa...
DAC
1999
ACM
14 years 11 months ago
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization
Partitioning and clustering are crucial steps in circuit layout for handling large scale designs enabled by the deep submicron technologies. Retiming is an important sequential lo...
Jason Cong, Honching Li, Chang Wu
GLVLSI
2003
IEEE
166views VLSI» more  GLVLSI 2003»
14 years 3 months ago
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
Edward Merlo, Kwang-Hyun Baek, Myung-Jun Choe
TPCD
1994
157views Hardware» more  TPCD 1994»
13 years 11 months ago
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization
Theorem proving techniques are particularly well suited for reasoning about arithmetic above the bit level and for relating di erent f abstraction. In this paper we show how a non-...
John W. O'Leary, Miriam Leeser, Jason Hickey, Mark...
ISLPED
2009
ACM
118views Hardware» more  ISLPED 2009»
14 years 4 months ago
Serial sub-threshold circuits for ultra-low-power systems
This paper explores the use of serial circuits for ultra-low-power sub-threshold systems. A serial system leads to a smaller design and higher utilization, yielding 40% active ene...
Sudhanshu Khanna, Benton H. Calhoun