1850 search results - page 253 / 370 » Power and performance optimization at the system level |
137
Voted
IROS
2009
IEEE
15 years 11 months ago
2009
IEEE
— In this paper the compliant low level control of a biologically inspired control architecture suited for bipedal dynamic walking robots is presented. It consists of elastic mec...
158
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TCAD
2008
15 years 4 months ago
2008
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
148
Voted
IEEEINTERACT
2003
IEEE
15 years 10 months ago
2003
IEEE
: The traditional framework for back-end compilation is based on the scope of functions, which is a natural boundary to partition an entire program for compilation. However, the si...
136
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ISCA
2009
IEEE
15 years 11 months ago
2009
IEEE
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...
171
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LCTRTS
2010
Springer
15 years 2 months ago
2010
Springer
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...