Sciweavers

734 search results - page 10 / 147
» Power balanced pipelines
Sort
View
83
Voted
IEICET
2008
51views more  IEICET 2008»
15 years 3 months ago
Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture
Hsin-Hung Ou, Soon-Jyh Chang, Bin-Da Liu
165
Voted
INFOCOM
2012
IEEE
13 years 6 months ago
SpeedBalance: Speed-scaling-aware optimal load balancing for green cellular networks
—This paper considers a component-level deceleration technique in BS operation, called speed-scaling, that is more conservative than entirely shutting down BSs, yet can conserve ...
Kyuho Son, Bhaskar Krishnamachari
102
Voted
ISLPED
2003
ACM
77views Hardware» more  ISLPED 2003»
15 years 9 months ago
Microprocessor pipeline energy analysis
The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wideissue, highly speculative cores. Microarchitectural speculation...
Karthik Natarajan, Heather Hanson, Stephen W. Keck...
128
Voted
HPCA
2009
IEEE
16 years 4 months ago
Elastic-buffer flow control for on-chip networks
This paper presents elastic buffers (EBs), an efficient flow-control scheme that uses the storage already present in pipelined channels in place of explicit input virtualchannel b...
George Michelogiannakis, James D. Balfour, William...
122
Voted
ICCAD
1998
IEEE
107views Hardware» more  ICCAD 1998»
15 years 8 months ago
Techniques for energy minimization of communication pipelines
The performance of many modern computer and communication systems is dictated by latency of communication pipelines. At the same time, power consumption is often another limiting ...
Gang Qu, Miodrag Potkonjak