734 search results - page 13 / 147 » Power balanced pipelines |
ICCD
2002
IEEE
14 years 5 months ago
2002
IEEE
High performance SoC requires nonblocking interconnections between an array of processors built on one chip. With the advent of deep sub-micron technologies, switches are becoming...
TSP
2008
13 years 8 months ago
2008
The focus of this paper is on VLIW instruction scheduling that minimizes the variation of power consumed by the processor during the execution of a target program. We use rough set...
APCSAC
2005
IEEE
14 years 2 months ago
2005
IEEE
Abstract. Power-balanced instruction scheduling for Very Long Instruction Word (VLIW) processors is an optimization problem which requires a good instruction-level power model for ...
ASPDAC
2004
ACM
14 years 2 months ago
2004
ACM
— We study the delays faced by instructions in the pipeline of a superscalar processor and its impact on power and performance. Instructions that are ready-on-dispatch (ROD) are ...
CORR
2008
Springer
13 years 8 months ago
2008
Springer
In this paper, we propose two new systematic ways to construct amicable orthogonal designs (AOD), with an aim to facilitate the construction of power-balanced orthogonal spacetime ...