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FPL
2000
Springer
124views Hardware» more  FPL 2000»
14 years 6 days ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
VLSID
2004
IEEE
138views VLSI» more  VLSID 2004»
14 years 9 months ago
Synthesis-driven Exploration of Pipelined Embedded Processors
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
ASPDAC
2010
ACM
143views Hardware» more  ASPDAC 2010»
13 years 6 months ago
A low latency wormhole router for asynchronous on-chip networks
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
Wei Song, Doug Edwards
CCGRID
2003
IEEE
14 years 1 months ago
Leveraging Non-Uniform Resources for Parallel Query Processing
Clusters are now composed of non-uniform nodes with different CPUs, disks or network cards so that customers can adapt the cluster configuration to the changing technologies and t...
Tobias Mayr, Philippe Bonnet, Johannes Gehrke, Pra...
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
14 years 8 days ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...