734 search results - page 22 / 147 » Power balanced pipelines |
EURODAC
1995
IEEE
14 years 5 days ago
1995
IEEE
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
ICCD
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
CSSE
2008
IEEE
13 years 10 months ago
2008
IEEE
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor core...
FCCM
2009
IEEE
14 years 14 days ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
SPAA
1997
ACM
14 years 24 days ago
1997
ACM
Pipelining has been used in the design of many PRAM algorithms to reduce their asymptotic running time. Paul, Vishkin, and Wagener (PVW) used the approach in a parallel implementat...