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ISCA
2006
IEEE
169views Hardware» more  ISCA 2006»
14 years 2 months ago
Balanced Cache: Reducing Conflict Misses of Direct-Mapped Caches
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
Chuanjun Zhang
TCAD
2008
127views more  TCAD 2008»
13 years 8 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
TMC
2010
150views more  TMC 2010»
13 years 7 months ago
Handling Mobility in Wireless Sensor and Actor Networks
— In Wireless Sensor and Actor Networks (WSANs), the collaborative operation of sensors enables the distributed sensing of a physical phenomenon, while actors collect and process...
Tommaso Melodia, Dario Pompili, Ian F. Akyildiz
IPPS
2007
IEEE
14 years 3 months ago
An Implementation of Page Allocation Shaping for Energy Efficiency
Main memory in many tera-scale systems requires tens of kilowatts of power. The resulting energy consumption increases system cost and the heat produced reduces reliability. Emerg...
Matthew E. Tolentino, Joseph Turner, Kirk W. Camer...
RTSS
2003
IEEE
14 years 1 months ago
Power-aware QoS Management in Web Servers
Power management in data centers has become an increasingly important concern. Large server installations are designed to handle peak load, which may be significantly larger than...
Vivek Sharma, Arun Thomas, Tarek F. Abdelzaher, Ke...