732 search results - page 11 / 147 » Power minimization using control generated clocks |
VTS
2000
IEEE
14 years 1 months ago
2000
IEEE
Excessive switching activity during scan testing can cause average power dissipation and peak power during test to be much higher than during normal operation. This can cause prob...
ICCD
2001
IEEE
14 years 5 months ago
2001
IEEE
Dynamic power is the main source of power consumption in CMOS circuits. It depends on the square of the supply voltage. It may significantly be reduced by scaling down the supply ...
GLVLSI
2000
IEEE
14 years 1 months ago
2000
IEEE
In this paper a wave-pipelining scheme is used to increase the performance of a router architecture. Wave-pipelining has a potential of significantly reducing clock cycle time an...
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
—A simple low-area and low-power clock frequency multiplier is proposed for Delay Locked Loop (DLL) based clock synthesizers. In this circuit, 2n voltage controlled delay lines (...
ICC
2007
IEEE
14 years 3 months ago
2007
IEEE
Abstract— Wireless topology control is the process of structuring the connectivity between network nodes to achieve some network-wide goal. This paper presents a cognitive networ...