732 search results - page 13 / 147 » Power minimization using control generated clocks |
ISLPED
2010
ACM
13 years 9 months ago
2010
ACM
Structured ASICs provide an exciting middle ground between FPGA and ASIC design methodologies. Compared to ASIC, structured ASIC based designs require lower non recurring engineer...
CDC
2009
IEEE
14 years 1 months ago
2009
IEEE
— We study a clock calibration problem for an ultra-low power timer on a sensor node platform. When the sensor is put into sleep mode, this timer is the only thing left running, ...
CDC
2009
IEEE
14 years 28 days ago
2009
IEEE
The aim of this study is to design a controller based on model predictive control (MPC) theory to smooth wind power generation along with the controlled storage of the wind energy ...
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
Abstract—This paper presents a low power 4-bit ADC for subGHz Ultra Wideband (UWB) receivers. The power efficiency is achieved by taking advantage of the low duty cycle feature o...
VLSID
2003
IEEE
14 years 9 months ago
2003
IEEE
Abstract-- In battery driven portable applications, the minimization of energy, average power, peak power, and peak power differential are equally important to improve reliability ...