732 search results - page 24 / 147 » Power minimization using control generated clocks |
ISCAS
2011
IEEE
13 years 18 days ago
2011
IEEE
—A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an a...
CHI
2006
ACM
14 years 9 months ago
2006
ACM
A problem with many of today's appliance interfaces is that they are inconsistent. For example, the procedure for setting the time on alarm clocks and VCRs differs, even amon...
ISLPED
2004
ACM
14 years 2 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
TWC
2010
13 years 3 months ago
2010
This paper studies the problem of finding a minimum-length schedule of a power-controlled wireless network subject to traffic demands and SINR (signal-to-interferenceplus-noise rat...
ISCAS
2008
IEEE
14 years 3 months ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...