732 search results - page 46 / 147 » Power minimization using control generated clocks |
MASCOTS
2007
13 years 10 months ago
2007
—Previously, we have developed a framework to perform systematic analysis of CSMA/CA based wireless MAC protocols. The framework first identifies protocol states that meet our ...
CODES
2003
IEEE
14 years 2 months ago
2003
IEEE
Boolean logic minimization is traditionally used in logic synthesis tools running on powerful desktop computers. However, logic minimization has recently been proposed for dynamic...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
DAC
2007
ACM
14 years 9 months ago
2007
ACM
The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
COMSWARE
2007
IEEE
14 years 3 months ago
2007
IEEE
— In wireless sensor networks, minimizing power consumption and at the same time maintaining desired properties in the network topology is of prime importance. In this work, we p...