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» Power minimization using control generated clocks
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ISCAS
2008
IEEE
77views Hardware» more  ISCAS 2008»
14 years 3 months ago
Impulse based scheme for crystal-less ULP radios
—This study describes a method of implementing a fully integrated ultra-low-power (ULP) radio for wireless sensor networks (WSNs). This is achieved using an ad hoc modulation sch...
Fabio Sebastiano, Salvatore Drago, Lucien Breems, ...
ECRTS
2007
IEEE
14 years 3 months ago
Thermal Faults Modeling Using a RC Model with an Application to Web Farms
Today’s CPUs consume a significant amount of power and generate a high amount of heat, requiring an active cooling system to support reliable operations. In case of cooling sys...
Alexandre P. Ferreira, Daniel Mossé, Jae C....
PODC
1997
ACM
14 years 1 months ago
Lazy Consistency Using Loosely Synchronized Clocks
Thispaperdescribesanewschemeforguaranteeingthattransactions in a client/server system observe consistent state while they are running. The scheme is presented in conjunction with ...
Atul Adya, Barbara Liskov
ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
14 years 3 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
14 years 3 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...