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» Power minimization using control generated clocks
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ITNG
2007
IEEE
14 years 3 months ago
Performance Analysis of Error Control Codes for Wireless Sensor Networks
In wireless sensor networks, the data transmitted from the sensor nodes are vulnerable to corruption by errors induced by noisy channels and other factors. Hence it is necessary t...
Gopinath Balakrishnan, Mei Yang, Yingtao Jiang, Yo...
ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
14 years 3 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
IAJIT
2010
141views more  IAJIT 2010»
13 years 7 months ago
Complex Gain Predistortion in WCDMA Power Amplifiers with Memory Effects
: Power amplifiers are essential components in communication systems and are inherently nonlinear. The nonlinearity creates spectral growth beyond the signal bandwidth, which inter...
Pooria Varahram, Somayeh Mohammady, Mohd Hamidon, ...
DATE
2004
IEEE
103views Hardware» more  DATE 2004»
14 years 15 days ago
A Novel Implementation of Tile-Based Address Mapping
Tile-based data layout has been applied to achieve various objectives such as minimizing cache conflicts and memory row switching activity. In some applications of tilebased mappi...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
14 years 3 months ago
Statistical model order reduction for interconnect circuits considering spatial correlations
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai,...