82 search results - page 6 / 17 » Power reduction techniques for Dynamically Reconfigurable Pr... |
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
The Translation Look-aside Buffer (TLB) is a very important part in the hardware support for virtual memory management implementation of high performance embedded systems. The TLB...
FPGA
2009
ACM
14 years 2 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
IEEEPACT
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper presents the Cameron Project 1 , which aims to provide a high level, algorithmic language and optimizing compiler for the development of image processing applications o...
CODES
2007
IEEE
13 years 11 months ago
2007
IEEE
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
IBMRD
2006
13 years 7 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...