35 search results - page 3 / 7 » Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optim... |
ARVLSI
2001
IEEE
13 years 11 months ago
2001
IEEE
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive curre...
VLSID
2005
IEEE
14 years 7 months ago
2005
IEEE
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
PATMOS
2007
Springer
14 years 1 months ago
2007
Springer
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...