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HPCA
2005
IEEE
14 years 3 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ICNP
2003
IEEE
14 years 3 months ago
Mobile Distributed Information Retrieval for Highly-Partitioned Networks
We propose and evaluate a mobile, peer-to-peer Information Retrieval system. Such a system can, for example, support medical care in a disaster by allowing access to a large colle...
Katrina M. Hanna, Brian Neil Levine, R. Manmatha
APSEC
2005
IEEE
14 years 3 months ago
Automated Refactoring of Objects for Application Partitioning
Distributed infrastructures are becoming more and more diverse in nature. An application may often need to be redeployed in various scenarios. Ideally, given an application design...
Vikram Jamwal, Sridhar Iyer
PRDC
2005
IEEE
14 years 3 months ago
Partitioned Cache Shadowing for Deep Sub-Micron (DSM) Regime
An important issue in modern cache designs is bridging the gap between wire and device delays. This warrants the use of more regular and modular structures to mask wire latencies....
Heng Xu, Arun K. Somani
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
14 years 2 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee