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CODES
2003
IEEE
14 years 3 months ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
AAAI
2007
14 years 11 days ago
Partial Revelation Automated Mechanism Design
In most mechanism design settings, optimal general-purpose mechanisms are not known. Thus the automated design of mechanisms tailored to specific instances of a decision scenario...
Nathanael Hyafil, Craig Boutilier
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
14 years 7 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
ICPADS
2006
IEEE
14 years 4 months ago
Scalable Hybrid Designs for Linear Algebra on Reconfigurable Computing Systems
—Recently, high-end reconfigurable computing systems that employ Field-Programmable Gate Arrays (FPGAs) as hardware accelerators for general-purpose processors have been built. T...
Ling Zhuo, Viktor K. Prasanna
IPPS
2003
IEEE
14 years 3 months ago
Targeting Tiled Architectures in Design Exploration
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas...