426 search results - page 29 / 86 » Power-Sensitive Multithreaded Architecture |
CATA
2004
13 years 10 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
IPPS
2007
IEEE
14 years 3 months ago
2007
IEEE
The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially...
IEEEPACT
1999
IEEE
14 years 1 months ago
1999
IEEE
We propose a multithreaded Java microcontroller-called Komodo microcontroller--with a new hardware event handling mechanism that allows handling of simultaneous overlapping events...
ICCD
2007
IEEE
14 years 17 days ago
2007
IEEE
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
IWMM
2000
Springer
14 years 8 days ago
2000
Springer
We investigate reference counting in the context of a multithreaded architecture by exploiting two observations: (1) reference-counting can be performed by a transformed program s...