426 search results - page 65 / 86 » Power-Sensitive Multithreaded Architecture |
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
Significant time is spent by companies trying to reproduce and fix bugs. BugNet and FDR are recent architecture proposals that provide architecture support for deterministic rep...
MICRO
2005
IEEE
14 years 1 months ago
2005
IEEE
— In this paper we investigate mapping stream programs (i.e., programs written in a streaming style for streaming architectures such as Imagine and Raw) onto a general-purpose CP...
ISSS
2002
IEEE
14 years 14 days ago
2002
IEEE
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...