426 search results - page 69 / 86 » Power-Sensitive Multithreaded Architecture |
EUROPAR
2009
Springer
14 years 2 months ago
2009
Springer
Moore’s Law suggests that the number of processing cores on a single chip increases exponentially. The future performance increases will be mainly extracted from thread-level par...
CLUSTER
2008
IEEE
14 years 2 months ago
2008
IEEE
—The current trend in clusters architecture leads toward a massive use of multicore chips. This hardware evolution raises bottleneck issues at the network interface level. The us...
COMPSAC
2008
IEEE
14 years 2 months ago
2008
IEEE
The rapid growth of Internet population leads to the shortage of IP addresses. The next generation IP protocol, IPv6, which extends the IP address length from 32 bits to 128 bits,...
HPCA
2008
IEEE
14 years 2 months ago
2008
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper describes our early experiences with a preproduction Cray XMT system that implements a scalable shared memory architecture with hardware support for multithreading. Unl...