46 search results - page 3 / 10 » Power-aware issue queue design for speculative instructions |
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated paramete...
ISCA
2002
IEEE
14 years 10 days ago
2002
IEEE
Instruction window size is an important design parameter for many modern processors. Large instruction windows offer the potential advantage of exposing large amounts of instructi...
ISCA
2002
IEEE
14 years 10 days ago
2002
IEEE
Increasing the number of instruction queue (IQ) entries in a dynamically scheduled processor exposes more instruction-level parallelism, leading to higher performance. However, in...
IEEEPACT
2000
IEEE
13 years 11 months ago
2000
IEEE
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
MICRO
1994
IEEE
13 years 11 months ago
1994
IEEE
Multiple issue of instructions occurs in superscalar and VLIW machines. This paper investigates a third type of machine design, which combines the advantages of code compatibility...