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ASPLOS
2008
ACM
15 years 6 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
14 years 8 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
DATE
2009
IEEE
178views Hardware» more  DATE 2009»
15 years 11 months ago
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration
As industry moves towards many-core chips, networks-on-chip (NoCs) are emerging as the scalable fabric for interconnecting the cores. With power now the first-order design constr...
Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Sam...
HICSS
2002
IEEE
148views Biometrics» more  HICSS 2002»
15 years 9 months ago
Barriers to a Wide-Area Trusted Network Early Warning System for Electric Power Disturbances
It is apparent that perturbations of the North American electric power grid follow the patterns and characteristics of Self Organized Critical (SOC) systems. Published studies sho...
Paul W. Oman, Jeff Roberts
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
15 years 10 months ago
Low power circuit design based on heterojunction tunneling transistors (HETTs)
The theoretical lower limit of subthreshold swing in MOSFETs (60 mV/decade) significantly restricts low voltage operation since it results in a low ON to OFF current ratio at low ...
Daeyeon Kim, Yoonmyung Lee, Jin Cai, Isaac Lauer, ...