The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Quorum-based Power Saving (QPS) protocols have been proposed for ad hoc networks (e.g., IEEE 802.11 ad hoc mode) to increase energy efficiency and prolong the operational time of...
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
The InTENsity PowerWall is a display system used for high-resolution visualization of very large volumetric data sets. The display is linked to two separate computing environments...
Alex W. Elder, Thomas Ruwart, Benjamin D. Allen, A...