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HPCA
2008
IEEE
16 years 4 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
SLIP
2009
ACM
15 years 11 months ago
Predicting the worst-case voltage violation in a 3D power network
This paper proposes an efficient method to predict the worst case of voltage violation by multi-domain clock gating in a three-dimensional (3D) on-chip power network considering l...
Wanping Zhang, Wenjian Yu, Xiang Hu, Amirali Shaya...
ICDCS
2008
IEEE
15 years 10 months ago
Fully Adaptive Power Saving Protocols for Ad Hoc Networks Using the Hyper Quorum System
Quorum-based Power Saving (QPS) protocols have been proposed for ad hoc networks (e.g., IEEE 802.11 ad hoc mode) to increase energy efficiency and prolong the operational time of...
Shan-Hung Wu, Ming-Syan Chen, Chung-Min Chen
153
Voted
ICS
2009
Tsinghua U.
15 years 9 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...
MSS
2000
IEEE
72views Hardware» more  MSS 2000»
15 years 8 months ago
The InTENsity PowerWall: A Case Study for a Shared File System Testing Framework
The InTENsity PowerWall is a display system used for high-resolution visualization of very large volumetric data sets. The display is linked to two separate computing environments...
Alex W. Elder, Thomas Ruwart, Benjamin D. Allen, A...