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CF
2005
ACM
15 years 6 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen
VTC
2007
IEEE
15 years 11 months ago
Performance Modelling and Analysis of the Sleep-Mode in IEEE802.16e WMAN
In this study, we analyze the sleep-mode operation for power management of a mobile station in the IEEE802.16e Wireless Metropolitan Access Network. For the analysis we use the M/...
Yunju Park, Gang Uk Hwang
ICC
2009
IEEE
207views Communications» more  ICC 2009»
15 years 11 months ago
Energy Efficient Collision Aware Multipath Routing for Wireless Sensor Networks
—Multipath routing can reduce the need for route updates, balance the traffic load and increase the data transfer rate in a wireless sensor network, improving the utilization of ...
Zijian Wang, Eyuphan Bulut, Boleslaw K. Szymanski
ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
16 years 1 months ago
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache
Abstract-- We deconstruct and compare the two dominant existing approaches for L1 data cache (L1D) error protection, with respect to performance, L2 cache bandwidth, power, and are...
Nathan Sadler, Daniel Sorin
VTS
2008
IEEE
77views Hardware» more  VTS 2008»
15 years 11 months ago
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty