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103
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ICCAD
1999
IEEE
89views Hardware» more  ICCAD 1999»
15 years 8 months ago
A bipartition-codec architecture to reduce power in pipelined circuits
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-J...
154
Voted
DAC
1997
ACM
15 years 8 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
131
Voted
TWC
2008
188views more  TWC 2008»
15 years 4 months ago
Joint power control and beamforming for cognitive radio networks
We consider a secondary usage of spectrum scenario where a secondary network coexists and/or shares the radio spectrum with a primary network to which the spectrum is licensed. The...
Habibul Islam, Ying-Chang Liang, Anh Tuan Hoang
COMCOM
2007
145views more  COMCOM 2007»
15 years 4 months ago
Jointly rate and power control in contention based MultiHop Wireless Networks
This paper presents a new algorithm for jointly optimal control of session rate, link attempt rate, and link power in contention based MultiHop Wireless Networks. Formulating the ...
Abdorasoul Ghasemi, Karim Faez
VLSISP
2008
103views more  VLSISP 2008»
15 years 2 months ago
Power Signature Watermarking of IP Cores for FPGAs
In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This ...
Daniel Ziener, Jürgen Teich