47 search results - page 6 / 10 » Precomputation-based Guarding for Dynamic and Leakage Power ... |
EUC
2008
Springer
13 years 8 months ago
2008
Springer
This paper studies the scheduling and assignment problem that minimizes the total energy including both dynamic and leakage energy for applications with loops on multi-voltage, mul...
MICRO
2005
IEEE
14 years 20 days ago
2005
IEEE
Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. In this paper, we first show that these power reduction techniques can b...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
ISLPED
1995
ACM
13 years 10 months ago
1995
ACM
The need to reduce the power consumption of the next generation of digital systems is clearly recognized. At the system level, power management is a very powerful technique and de...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...