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» Predictable performance in SMT processors
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EXPCS
2007
14 years 22 days ago
Introducing entropies for representing program behavior and branch predictor performance
Predictors are inherent components of state-of-the-art microprocessors. Branch predictors are discussed actively from diverse perspectives. Performance of a branch predictor large...
Takashi Yokota, Kanemitsu Ootsu, Takanobu Baba
MICRO
1998
IEEE
139views Hardware» more  MICRO 1998»
14 years 1 months ago
A Dynamic Multithreading Processor
We present an architecture that features dynamic multithreading execution of a single program. Threads are created automatically by hardware at procedure and loop boundaries and e...
Haitham Akkary, Michael A. Driscoll
IPPS
2007
IEEE
14 years 3 months ago
Power-Aware Speedup
Power-aware processors operate in various power modes to reduce energy consumption with a corresponding decrease in peak processor throughput. Recent work has shown power-aware cl...
Rong Ge, Kirk W. Cameron
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
14 years 1 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
14 years 2 months ago
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...