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» Predictable performance in SMT processors
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ICDE
2011
IEEE
270views Database» more  ICDE 2011»
13 years 15 days ago
Real-time pattern matching with FPGAs
— We demonstrate a hardware implementation of a complex event processor, built on top of field-programmable gate arrays (FPGAs). Compared to CPU-based commodity systems, our sol...
Louis Woods, Jens Teubner, Gustavo Alonso
MICRO
2010
IEEE
119views Hardware» more  MICRO 2010»
13 years 6 months ago
A Predictive Model for Dynamic Microarchitectural Adaptivity Control
Abstract--Adaptive microarchitectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resou...
Christophe Dubach, Timothy M. Jones, Edwin V. Boni...
IPPS
2007
IEEE
14 years 3 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
FGCS
2006
74views more  FGCS 2006»
13 years 8 months ago
A performance model of non-deterministic particle transport on large-scale systems
In this work we present a predictive analytical model that encompasses the performance and scaling characteristics of a nondeterministic particle transport application, MCNP (Mont...
Mark M. Mathis, Darren J. Kerbyson, Adolfy Hoisie
IPPS
2007
IEEE
14 years 3 months ago
Modeling of NAMD's Network Input/Output on Large PC Clusters
This study examined the interplay among processor speed, cluster interconnect and file I/O, using parallel applications to quantify interactions. We focused on a common case wher...
Nancy Tran, Daniel A. Reed