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» Predictable performance in SMT processors
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ECRTS
2006
IEEE
14 years 1 months ago
WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Isabelle Puaut
ICS
2000
Tsinghua U.
13 years 11 months ago
Hardware-only stream prefetching and dynamic access ordering
Memory system bottlenecks limit performance for many applications, and computations with strided access patterns are among the hardest hit. The streams used in such applications h...
Chengqiang Zhang, Sally A. McKee
ICCD
2004
IEEE
87views Hardware» more  ICCD 2004»
14 years 4 months ago
Fetch Halting on Critical Load Misses
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...
Nikil Mehta, Brian Singer, R. Iris Bahar, Michael ...
MICRO
1999
IEEE
115views Hardware» more  MICRO 1999»
13 years 12 months ago
Fetch Directed Instruction Prefetching
Instruction supply is a crucial component of processor performance. Instruction prefetching has been proposed as a mechanism to help reduce instruction cache misses, which in turn...
Glenn Reinman, Brad Calder, Todd M. Austin
ASPLOS
2010
ACM
14 years 20 days ago
Modeling GPU-CPU workloads and systems
Heterogeneous systems, systems with multiple processors tailored for specialized tasks, are challenging programming environments. While it may be possible for domain experts to op...
Andrew Kerr, Gregory F. Diamos, Sudhakar Yalamanch...