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ARITH
1999
IEEE
13 years 11 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
ISHPC
1999
Springer
13 years 11 months ago
Instruction-Level Microprocessor Modeling of Scientific Applications
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...
Kirk W. Cameron, Yong Luo, James Scharzmeier
ICS
1989
Tsinghua U.
13 years 11 months ago
Control flow optimization for supercomputer scalar processing
Control intensive scalar programs pose a very different challenge to highly pipelined supercomputers than vectorizable numeric applications. Function call/return and branch instru...
Pohua P. Chang, Wen-mei W. Hwu
ASAP
2007
IEEE
133views Hardware» more  ASAP 2007»
13 years 11 months ago
An Efficient Hardware Support for Control Data Validation
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...
Yong-Joon Park, Zhao Zhang, Gyungho Lee
ADBIS
2006
Springer
165views Database» more  ADBIS 2006»
13 years 11 months ago
Fragmenting XML Documents via Structural Constraints
Abstract. XML query processors suffer from main-memory limitations that prevent them from processing large XML documents. While content-based predicates can be used to project down...
Angela Bonifati, Alfredo Cuzzocrea, Bruno Zinno