492 search results - page 93 / 99 » Predictable performance in SMT processors |
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
MICRO
2007
IEEE
14 years 1 months ago
2007
IEEE
Program runtime characteristics exhibit significant variation. As microprocessor architectures become more complex, their efficiency depends on the capability of adapting with wor...
RTSS
2006
IEEE
14 years 1 months ago
2006
IEEE
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
CF
2004
ACM
14 years 27 days ago
2004
ACM
Although many defense mechanisms against buffer overflow attacks have been proposed, buffer overflow vulnerability in software is still one of the most prevalent vulnerabilities e...
VLSISP
2008
13 years 7 months ago
2008
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particula...