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» Predicting Lattice Reduction
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152
Voted
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
15 years 9 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
122
Voted
CHI
2010
ACM
15 years 9 months ago
vSked: evaluation of a system to support classroom activities for children with autism
Visual schedules—the use of symbols to represent a series of activities or steps—have been successfully used by caregivers to help children with autism to understand, structur...
Sen H. Hirano, Michael T. Yeganyan, Gabriela Marcu...
117
Voted
ISQED
2003
IEEE
134views Hardware» more  ISQED 2003»
15 years 9 months ago
Concurrent Fault Detection in Random Combinational Logic
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circui...
Petros Drineas, Yiorgos Makris
116
Voted
ISLPED
2003
ACM
113views Hardware» more  ISLPED 2003»
15 years 9 months ago
Reducing power density through activity migration
Power dissipation is unevenly distributed in modern microprocessors leading to localized hot spots with significantly greater die temperature than surrounding cooler regions. Exc...
Seongmoo Heo, Kenneth C. Barr, Krste Asanovic
113
Voted
DNA
2001
Springer
15 years 8 months ago
The Fidelity of the Tag-Antitag System
In the universal DNA chip method, target RNAs are mapped onto a set of DNA tags. Parallel hybridization of these tags with an indexed, complementary antitag array then provides an ...
John A. Rose, Russell J. Deaton, Masami Hagiya, Ak...